This invention relates to a semiconductor device and a method of fabrication of the same, and more particularly to the structure and fabricating method of a transistor device suited to a high speed and high integration trend of semiconductor integrated circuit such as bipolar types.
In the field of recent bipolar integrated circuits, various new technologies have been proposed for the improvement of the switching speed of the transistor. Principal improving methods employing such technologies may include (i) a method of shortening the electron transit time in the base by forming the internal base of a vertical NPN transistor in a small thickness in the depthwise direction of the base, and (ii) a method of lowering the resistance of a parasitic base so as to decrease the delay time due to coupling of the parasitic base resistance inserted in series to the intrinsic base and the base input capacitance. As the method of lowering the resistance of the parasitic base, the parasitic base region for taking out the electrode is formed by diffusion of impurities of higher concentration than in the intrinsic base, and it is used as extrinsic base, which is known generally as the graft base method. For example, in the International Electron Device Meeting Digest of Technical Papers, 1984, pp. 753-756, a structure is disclosed of the formation of a vertical NPN transistor, in which the extrinsic base formed beneath a thermal oxidation film and the intrinsic base formed from the opening of the thermal oxidation film are connected with each other in the vicinity of the end portion of the thermal oxidation film. For example, in the structure of a vertical NPN transistor shown in FIG. 8, an n-type buried layer 210 and an n-type epitaxial layer 212 are formed on a p-type semiconductor layer 200, and a depletion layer 222 is formed on the epitaxial layer 212. In conjunction with p-type extrinsic bases 220A, 220B are formed p-type regions 240A, 240B, 240C, which become thin intrinsic bases, being made up by boron ion injection from the opening of silicon oxide films 230A, 230B, and an n-type region 260, which becomes an emitter. Here, supposing the specific resistance of the n-type epitaxial layer to be about 1 .OMEGA.-cm, the depth A of the extrinsic base from the principal plane of epitaxial layer to be about 0.6 .mu., the depth B of intrinsic base to be about 0.2 .mu., the depth C of emitter to be about 0.1 .mu., the length D of depletion layer to be about 1 .mu., the opening width between silicon oxide films 230A, 230B formed by selective oxidation to be about 1 .mu., and the lateral diffusion length of p-type regions 230A, 230B formed by diffusion immediately before selective oxidation to be about 0.6 82 , the effective width X of the intrinsic base region 240B not canceled by the lateral diffusion of the extrinsic bases 230A, 230B is very narrow, about 0.2 .mu., and the length Y of the depletion layer immediately beneath the intrinsic base is about 1.2 .mu., that is, 0.2 .mu. longer.
As shown in FIG. 8, the width X of the intrinsic base region 240B which becomes the collector current passage of the vertical NPN transistor is about 0.2 .mu., that is, 1/5 of about 1.0 .mu. of the opening width of the emitter. As a result, the collector current becomes substantially small, and drop of current amplification factor is extreme. On the other hand, the length Y of the depletion layer 222 of the collector right beneath the intrinsic base region becomes about 20% larger, which causes an increase the transit time of electrons in the collector depletion layer. Thus, if it is attempted to form the diffusion regions 220A, 220B high in the impurity concentration by ordinary self-aligned process in order to lower the resistance of the extrinsic base, the switching speed is reduced due to the lack of drive capacity of the collector and the overgrowth of collector-base depletion layer, and it was practically impossible to form a fine emitter suited to the high speed and high integration trend.
As stated above, when high concentration impurities of the extrinsic base invade into the intrinsic base, problems occur, but different problems are also experienced in a different situation. That is, for the high speed operation of bipolar transistor, shallow an intrinsic base and a low resistance of the extrinsic base must be realized at the same time. As the intrinsic base becomes smaller in depth, the increase of squeeze resistance of the intrinsic base is likely to occur, and in order to reduce this effect, usually, the emitter width is narrowed. In this case, however, if the concentration of impurities in the extrinsic base is raised, the impurity atoms invade into the intrinsic base to modify the profile of the impurities in the intrinsic base, thereby decreasing the current amplification factor in DC and increasing the base transit time of electrons in AC. To suppress these phenomena, no other means are known than to lower the impurity concentration in the extrinsic base and to decrease the diffusion in the lateral direction of the base. According to this method, invasion of the extrinsic base may be controlled, but when the depth of the intrinsic base is made as small as 150 nanometers, the following structural or manufacturing problems occur. That is, since the opening end formed at the beak-shaped end of oxide film fluctuates unstably due to etching during processing, the connection of the intrinsic base and extrinsic base becomes unstable. Or when the connection is poor, since the lateral diffusion of the intrinsic base beneath this beak is small, the effective base width in the lateral direction becomes narrow, so that a punch-through leakage current is likely to occur between the collector and emitter. For example, as shown in FIG. 9 A, an N-type buried layer 102 is formed on a P-type silicon semiconductor substrate 100, and further an N-type epitaxial semiconductor layer 104 is formed, then a thin thermal oxide film 108 of about 20 nanometers in thickness is formed. On this thermal oxide film 108, a silicon nitride film pattern 110 of about 100 nanometers in thickness is formed, and using this pattern 110 as a mask, boron ions are implanted into the epitaxial semiconductor layer 104 at a dose of 2.times.10.sup.15 /cm.sup.2, thereby forming a P-type semiconductor region 116 which becomes an extrinsic base. Moreover, as shown in FIG. 9 B, thermal oxidation is effected by using an oxidation resistant silicon nitride film pattern 110 as a mask, and an oxide film 122 of about 250 nanometers in thickness is formed, and after removing the silicon nitride film pattern 110 and oxide film 108 and making an opening for the emitter, a polycrystalline silicon film is deposited on the entire surface, and by patterning it, a polycrystalline silicon film pattern 124 is formed. Next, by implanting boron ions into this polycrystalline silicon film pattern 124 at a dose of 2.times.10.sup.14 /cm.sup.2, and heating, a P-type semiconductor region 126 is formed having a thickness of about 150 nanometers, which becomes an intrinsic base. Later, similarly, by implanting arsenic ions into this polycrystalline silicon film pattern 124, and by heat treatment, an N-type semiconductor region 128 is formed having a thickness of about 50 nanometers, which becomes an emitter. According to this manufacturing method, the end portion of the oxide film pattern 112 shown in FIG. 9 B is shaped like a bird's beak, and by this end portion shaped like a bird's beak, connection between the extrinsic base 116 and the intrinsic base 126 becomes difficult. In this background, therefore, a novel transistor structure and its manufacturing method to solve the structural and manufacturing problems derived from the instability of connection between extrinsic base and intrinsic base have been desired.